A delay time of a signal is adjusted in various semiconductor apparatuses (Patent Literatures 1 to 3). In the DDR 3 memory interface (DDR: Double Data Rate) that is standardized by JEDEC (Joint Electron Device Engineering Council) as a standard of DRAM (Dynamic Random Access Memory), a fly-by topology is employed in a connection between a memory controller and DIMM (Dual Inline Memory Module). Therefore, so-called write leveling is defined for adjusting a delay time of a data strobe signal DQS that is output from the memory controller to each of a plurality of memory elements included in the DIMM (Patent Literature 4).
FIG. 11 is identical to FIG. 19 of Patent Literature 4 and schematically shows an example of a connection between the memory controller 90 and the DIMM 91 that are compliant with the DDR3 memory interface. As shown in the drawing, among the signal lines connecting between the memory controller 90 and the DIMM 91, the signal line for a clock signal CK, an address signal Add, and a command signal CMD is connected between the memory controller 90 and n (n: a natural number of two or greater) memory elements (SDRAM: Synchronous Dynamic Random Access Memory) 92-1 to 92-n in the DIMM 91 by daisy chain wiring. Further, the signal lines for the data signal DQ and the data strobe signal DQS are connected between the memory controller 90 and the respective SDRAMs 92-1 to 92-n in the DIMM 91.
In the following explanation, as for codes to represent the SDRAMs, when it is necessary to identify a specific one of the plurality of SDRAMs, codes 92-1 to 92-n shall be used, while when any given SDRAM is specified, a code 92 shall be used.
Further, as for codes to represent data signals, when it is necessary to identify a specific one of the plurality of data signals, codes DQ-1 to DQ-n shall be used, while when any given data signal is specified, a code DQ shall be used.
Similarly, as for codes to represent data strobe signals, when it is necessary to identify a specific one of the plurality of data strobe signals, codes DQS-1 to DQS-n shall be used, while when any given data strobe signal is specified, a code DQS shall be used.
Due to a propagation delay caused by the daisy chain wiring of the signal line for a clock signal CK, clock signals CK that are output from the memory controller 90 are unable to simultaneously arrive at all of the SDRAMs 92-1 to 92-n. For example in the JEDEC standard, as for the external dimensions of the DIMM 91, the length L1 is defined as 133 mm. Therefore, between the SDRAM 92-1 disposed at one end of the DIMM 91 in the length direction and the SDRAM 92-n disposed at the other end of the DIMM 91 in the length direction, there is a difference in arrival times of about 1 ns (7 ps/mm*133 mm=931 ps).
Accordingly, the JEDEC standard defines the write leveling to be used in the DDR3 memory interface. Referring to FIG. 12 (FIG. 20 of Patent Literature 4), a brief explanation of the write leveling shall be given.
The term “write leveling” refers to the function of sampling the clock signal CK by using the data strobe signal DQS output from the memory controller 90, detecting the phase relationship between the data strobe signal DQS and the clock signal CK, and adjusting a delay time of the data strobe signal DQS. The write leveling function is implemented, as shown in FIG. 12, by incorporating variable delay circuits 93-1 to 93-n, which can change respective delay times of the data strobe signals DQS-1 to DQS-n, in the memory controller 90 corresponding to the plurality of SDRAMs 92-1 to 92-n, respectively
Hereinafter, as for codes to represent delay circuits, when it is necessary to identify a specific one of the plurality of delay circuits, codes 93-1 to 93-n shall be used, while when any given delay circuit is specified, a code 93 shall be used.
Specifically, a CPU (Central Processing Unit) not shown in the drawings sets delay times t1-1 to t1-n for the data strobe signals DQS-1 to DQS-n that are output to the respective SDRAMs 92 based on the data signals DQ-1 to DQ-n that are output from the SDRAMs 92-1 to 92-n, respectively. In this manner, the data strobe signals DQS-1 to DQS-n are adjusted such that they are input to the SDRAMs 92-1 to 92-n, respectively, almost at the same time as the clock signals CK.
That is, for example, at the point when the write leveling is completed, the delay circuits 93-1 to 93-n delay the data strobe signals DQS by only the delay times t1-1 to t1-n, respectively, and the data strobe signals DQS and the clock signals CK are input to the SDRAMs 92-1 to 92-n with their phases aligned.
Note that the write leveling is performed at the time of initializing a memory device that includes the DDR3 memory interface. That is, when the initialization including the write leveling is completed, the delay times t1-1 to t1-n are determined, and the clock signals CK and the data strobe signals DQS are input to the respective SDRAMs with their phases aligned.